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Combined Synopsis/Solicitation Expired 2 notices 3 documents

CHIPS High-Throughput High-Resolution X-ray Laminography/Tomography System for Advanced Packaged Semiconductor Devices and Substrates 1333ND26QNB030031

Solicitation 1333ND26QNB030031 Copied Notice ID fcad963625ca4b36b09c834176fbc194 Copied COMMERCE, DEPARTMENT OF — DEPT OF COMMERCE NIST
SAM.gov
Posted
Feb 24, 2026
Deadline
Mar 09, 2026
Set-aside
None
NAICS
334413
PSC
6640

Summary

AI-generated · Feb 13, 2026

CHIPS high-throughput, high-resolution X-ray laminography/tomography system for advanced packaged semiconductor devices and substrates enables non-destructive 3D imaging and inspection.

Details reside in Attachment 1 - Statement of Work and Attachment 2 - Applicable Provisions and Clauses accompanying the Combined Synopsis/Solicitation.

See Combined Synopsis Solicitation_1333ND26QNB030031, Attachment 1 - Statement of Work, and Attachment 2 - Applicable Provisions and Clauses attachments for solicitation details.

From Combined Synopsis/Solicitation posted on Feb 12, 2026

Amendment 0001: Amendment changes include the following: The required response date is extended from February 26, 2026 to March 9, 2026 No Statement of work change Questions and Answers: Question1: Is there a cleanroom specification? NIST Response: No. The instrument will be installed in a general purpose lab in the advanced measurement laboratory facility, but not within a cleanroom. Question 2: Are you flexible on the footprint (size/dimension) NIST Response: NIST expects the analytical instrument (source, stages, detectors, and shielded enclosure) to fit within the footprint specified by 10.2. Additional space is available in the lab around the instrument for service access, and for support equipment (including chase space for air compressor/dryer if required, and a work area in the lab for control and analysis PCs). Question 3: Are the devices in JEDEC Trays? NIST Response: Typically no. NIST requires significant flexibility to load samples that are within the size envelope described by specification 5. Samples will include full wafers, coupons (partial wafers), individual or groups of packaged devices, as well as atypical sample geometries. To meet requirement 5.1, vendors must include 5 sample carriers that are compatible with the automated loading system. Carriers supporting a JEDEC tray is only one possible way to meet that requirement. See Combined Synopsis Solicitation_1333ND26QNB030031, Attachment 1 - Statement of Work, and Attachment 2 - Applicable Provisions and Clauses attachments for solicitation details.

From Combined Synopsis/Solicitation posted on Feb 24, 2026

Notice history

2
  1. Combined Synopsis/Solicitation Posted Feb 12, 2026 View
  2. Combined Synopsis/Solicitation LATEST Posted Feb 24, 2026
    • Description: Description was updated
    • Response Deadline: Feb 26, 2026Mar 09, 2026

Details

Solicitation number 1333ND26QNB030031
Notice ID fcad963625ca4b36b09c834176fbc194
Notice type Combined Synopsis/Solicitation
Product / Service (PSC) 6640
NAICS 334413
Place of performance Gaithersburg, Maryland
Archive date Mar 24, 2026

Award Information

Not yet awarded

Contacts

primary
Tracy Retterer

Email

secondary
Donald Collie

Email

Agency

COMMERCE, DEPARTMENT OF
NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY
DEPT OF COMMERCE NIST

Place of Performance

Gaithersburg, Maryland 20899
USA

Dates

Posted Feb 24, 2026 5 months ago
Last Updated Aug 06, 2026 1 day ago
Due Mar 09, 2026 4 months ago